1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for fabricating a semiconductor device in which gate resistance is easily reduced and a gate is easily defined when forming a dual gate is.
2. Background of the Related Art
Generally, a dynamic random access memory (DRAM) tends toward a rapid increase of high packing density. The increase in high packing density accompanies a reduction of the area and size of the device. The reduction in the size of the device causes a degradation of device characteristics.
With the decrease of a channel, the gate is reduced. For this reason, gate resistance is increased. An increase in the gate resistance is directly related to the speed of the device. In the case of a buried channel PMOS transistor based on N+ polysilicon, the degradation of the device due to a short channel effect becomes serious.
To solve such a problem, n-polysilicon and p-polysilicon are respectively used as gate formation materials for NMOS and PMOS transistors. To improve the gate resistance, either a polycide gate or a salicide gate is formed.
However, in view of a later trend in which the design rule is reduced, it is difficult to define a gate, especially in the case of a polycide, if the aspect ratio is increased.
A related method for fabricating a semiconductor device will be described with reference to the accompanying drawings.
As shown in FIG. 1a, device isolation regions 12 are formed in a semiconductor substrate 11 of a first conductive type, utilizing the trench isolation process. A well region 13 is selectively formed within the semiconductor substrate 11 by ion implantation of a second conductive type.
As shown in FIG. 1b, a gate insulating film 14, a polysilicon layer 15 on which impurity ions are not doped, and a cap insulating film 16 are sequentially formed on the entire surface of the semiconductor substrate 11. Then, a first mask layer 17 is formed for gate doping of a PMOS transistor, and impurity ions of the first conductive type, for example, boron (B) ions, are doped on the polysilicon layer 15 by impurity ion implantation using the first mask layer 17.
As shown in FIG. 1c, the first mask layer is removed, and a second mask layer 17a is formed for gate doping of an NMOS transistor. Impurity ions of the second conductive type, for example, arsenic (As) ions or phosphorous (P) ions are doped on the polysilicon layer 15 by impurity ion implantation using the second mask layer 17a. 
Subsequently, as shown in FIG. 1d, the polysilicon layer 15 is patterned by a photo etching process to form a gate electrode 15a of the PMOS transistor and a gate electrode 15b of the NMOS transistor.
As shown in FIG. 1e, a lightly doped drain (LDD) region 18a of the first conductive type is formed within the surface of the semiconductor substrate 11 at both sides of the gate electrode 15a of the PMOS transistor, and an LDD) region 18b of the second conductive type is formed within the surface of the semiconductor substrate 11 at both sides of the gate electrode 15b of the NMOS transistor. At this time, the LDD region 18a of the first conductive type and the LDD region 18b of the second conductive type are selectively formed using a mask.
As shown in FIG. 1f, an insulating film is deposited on the entire surface including the gate electrode 15a of the PMOS transistor and the gate electrode 15b of the NMOS transistor.
The insulating film is then etched back to form sidewalls 19 at both sides of the gate electrodes 15a and 15b. Subsequently, first source/drain regions 20 and 20a are formed within the substrate at both sides of the gate electrode 15a of the PMOS transistor by conducting a heavily doped impurity ion implantation of the first conductive type. Also, second source/drain regions 21 and 21a are formed within the substrate at both sides of the gate electrode 15b of the NMOS transistor by conducting a heavily doped impurity ion implantation of the second conductive type. Thus, the related art process for fabricating a semiconductor device is completed. Thus, the fire source/drain regions 20 and 20a and the second source/drain regions 21 and 21a are formed by impurity ion implantation using respectively different masks.
However, the related art method for fabricating a semiconductor device has several problems.
First, after the undoped polysilicon layer is formed, the boron ions, having a high diffusion speed, are diffused into the channel region through the grain and tie grain boundary of the polysilicon layer during ion implantation for the formation of P polysilicon and N polysilicon. This increases channel resistance irregularly.
Second, in case where the silicide layer is formed on the gate electrode to reduce the gate resistance, it is necessary to remove the cap insulating film, thereby causing an inconvenience. In the case where the silicide is formed in a state where the cap insulating film is not completely removed the gate resistance is increased rather than reduced. In other words, in a general tendency in which the area of the gale electrode gradually becomes smaller, the formation of such an unstable silicide layer causes the gate resistance to be increased.
Accordingly, the present invention is directed to a method for fabricating a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Accordingly, an object of the present invention is to provide a semiconductor device and a method for fabricating a semiconductor device in which channel resistance is prevented from occurring due to impurity ion diffusion and a reduction in gate resistance, thereby improving speed characteristics of the device.
Additional advantages, objects, and features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill n the art upon examination of the following or may be learned from the practice of the invention.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method for forming a dual gate of a semiconductor device according to the present invention includes the steps of: forming a polysilicon layer on a semiconductor substrate; selectively forming an impurity ion layer of a first conductive type and an impurity ion layer of a second conductive type on a lower surface of the polysilicon layer, polishing the polysilicon layer; forming a low resistance metal layer on the polished potysilicon layer, forming a first gate electrode and a second gate electrode by an etching process using a gate mask; and forming source/drain regions of the first conductive type in the substrate at both sides of the first gate electrode and source/drain regions of the second conductive type in the substrate at both sides of the second gate electrode.
The process for selectively forming the impurity ion layer of the first conductive type and the impurity ion layer of the second conductive type on the lower surface of the polysilicon layer includes the steps of forming a first mask to partially expose the polysilicon layer, implanting impurity ions of the first conductive type into the lower surface of the exposed polysilicon layer by controlling the ion implantation energy, removing the first mask, forming a second mask to expose the polysilicon layer on which the impurity ions of the first conductive type are not doped, and implanting impurity ions of the second conductive type into the lower surface of the exposed polysilicon layer by controlling the ion in plantation energy.
The polishing step is performed by a chemical mechanical polishing (CMP) process, and the low resistance metal layer is either tungsten (W) or titanium (Ti).
Also, before forming the low resistance metal layer, the step of forming a barrier layer on the polysilicon layer is further provided.
The first gate electrode is formed of the polysilicon layer on which the impurity ions of the firs conductive type are doped, with the low residence metal layer disposed thereon, and the second gate electrode is foiled of the polysilicon layer on which the impurity ions of the second conductive type are doped with the low resistance metal layer disposed thereon.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not intended to limit the scope of the present invention.